I’ve been a trader and investor for 44 years. I left Wall Street long ago—-once I understood that their obsolete advice is designed to profit them, not you.
Today, my firm manages around $5 billion in ETFs, and I don’t answer to anybody. I tell the truth because trying to fool investors doesn’t help them, or me.
In Daily H.E.A.T. , I show you how to Hedge against disaster, find your Edge, exploit Asymmetric opportunities, and ride major Themes before Wall Street catches on.
Table of Contents
H.E.A.T.
3:1 Wafer capacity HBM consumes vs. DDR5 — the arithmetic behind the shortage | 90–95% Conventional DRAM contract price rise Q1 2026 (TrendForce) | 9 Routes Engineering detours being built around the memory hierarchy | 2027–28 Earliest meaningful commodity DRAM supply relief (industry consensus) |
The memory shortage is not just a supply problem. It is becoming an architecture problem.
On June 15, AMD announced it had acquired MEXT, a memory-optimization startup whose software is designed to make flash behave more like DRAM. AMD's stated rationale: improve memory optimization, reduce total cost of ownership, and make flash perform more like DRAM for compute infrastructure.
That is the signal.
AMD did not buy a DRAM supplier. It bought a way to reduce how much DRAM customers need.
In a normal memory cycle, that would be a niche efficiency tool. In this cycle, it is something bigger: a public admission that the memory hierarchy is no longer fixed. The AI buildout is not waiting for DRAM supply to normalize. It is building detours.
The mechanism behind the shortage matters. HBM — the stacked DRAM that feeds GPU clusters — consumes roughly three times the wafer capacity of standard DDR5 to produce equivalent bits, by Micron's own published figures. As Samsung, SK hynix, and Micron reallocate capacity toward HBM, commodity DRAM gets squeezed out of fab space. TrendForce put first-quarter conventional DRAM contract prices at +90–95% quarter over quarter, with a further 58–63% rise projected for Q2. This is not a demand spike. It is a structural supply reallocation that does not reverse when demand cools.
New fabs don't arrive until 2027. The ones that do arrive go to HBM first. The Big 3 have publicly committed to not repeating the capacity race that broke profitability in prior cycles. And AI workloads are not compressing.
What is happening instead is that nine separate engineering tracks are converging to route around the bottleneck — some using different materials, some moving computation to the data, some reducing how much memory the system needs in the first place. Intel's CEO said there is no stability until 2028. AMD bought a tiering startup. Those two facts, placed next to each other, define the investment landscape for the next two years.
There is a second pressure point: China is not only routing around the memory tax through software. It is building domestic DRAM supply underneath its own compute stack. Reuters reported on June 29 that CXMT has signed a long-term server DRAM supply deal with Tencent worth over $2.94 billion. CXMT held approximately 7.7% global DRAM share in 2025 and is planning to roughly double capacity. The memory tax is being attacked from both sides: system architecture reduces demand, while China adds politically protected supply.
"The memory tax will not be solved by one new fab or one new memory type. It will be arbitraged by interfaces: CXL controllers, tiering software, NAND-adjacent memory, module IP, packaging, and purpose-built inference chips. Memory producers win the shortage. Interface owners win the redesign." |
PART I: THE ANATOMY OF THE MEMORY TAX
Start with the hierarchy. A computer's memory is stacked in layers. At the top: SRAM cache, fast and tiny. Below it: DRAM, the working memory where active computation lives. Below that: NAND flash, cheap and slow. The memory tax is what happens when the top two floors of that hierarchy get pulled in opposite directions simultaneously.
HBM is the most profitable product in the memory industry. But making it is extraordinarily capital-intensive — not because the die itself is expensive, but because each HBM part consumes the wafer capacity that would otherwise produce three commodity DDR5 parts. As HBM allocation expands from roughly 18% of wafer starts in 2025 to an estimated 30% by 2027, the standard DRAM destined for phones, PCs, and servers gets physically displaced.
The result is a price inversion that cannot appear in a normal supply-demand market: DDR4 became more expensive than DDR5 in 2026. An older, less capable product commanded a premium over a newer one — not because of demand, but because its specific supply segment had been vacated wholesale.
The shortage is not resolving cleanly. It is dissolving unevenly as customers build detours around the most expensive part of the memory stack. Those detours are the investment story.
THE TWO ASYMMETRIES THAT MAKE NAND THE DEFAULT DETOUR MEDIUM Cost: NAND is 5-50x cheaper per bit than DRAM — an order-of-magnitude gap that optimization cannot close. Process: NAND grows capacity via vertical cell stacking, not EUV scaling. It operates entirely outside the lithography bottleneck throttling everything else. NAND is the biggest single beneficiary of the detour economy — but not the only one. Some detours replace DRAM with NAND. Some pool DRAM more efficiently. Some compress demand. Some move compute to the data. The common denominator is not NAND. It is interface control. |
PART II: THE NINE ROUTES — BAND BY BAND
The nine routes engineers are building around the memory tax fall into three bands, ordered by timeline. Two additional tracks — SRAM inference chips and new-material memory — sit outside the nine as strategic watchlist items. The earliest relief arrives now. The deepest structural redesign arrives after 2028.
BAND 1 — CHANGE THE MEDIUM
Track 1: High Bandwidth Flash (HBF) | 2027–2028
Beneficiaries: Sandisk, SK hynix, Samsung, packaging
HBF is a NAND-based memory layer positioned between HBM and SSDs in the hierarchy. Sandisk and SK hynix announced a global standardization effort under the Open Compute Project in February 2026 — which means HBF is still a standardization and commercialization path, not an immediately deployed product cycle. The key point is not that NAND becomes DRAM. The key point is that NAND becomes close enough to the compute path to absorb inference workloads that would otherwise require expensive DRAM capacity. For workloads where capacity and cost per bit matter more than DRAM-class latency — KV cache overflow in long-context inference being the clearest case — HBF is a structurally sound architecture bet. Beneficiaries: Sandisk, SK hynix, Samsung, advanced packaging suppliers.
Track 2: NAND Tiering / Enterprise SSD as Memory Adjunct | 2026–2027
Beneficiaries: Sandisk, Kioxia, Samsung, enterprise SSD suppliers
Distinct from HBF's standardization effort, enterprise SSD deployments are already being used as a software-managed memory tier in production AI infrastructure. The gap between NAND and DRAM narrows when a tiering layer predicts access patterns accurately. This track feeds directly into Track 7 (Predictive Tiering). The NAND capacity advantage holds: stacking cells vertically adds bits without EUV. Enterprise SSD attach rates in AI server racks are rising regardless of whether HBF reaches standardization.
BAND 2 — REDUCE DATA MOVEMENT
Track 3: PIM / PNM (Processing In / Near Memory) | 2028–2030
Beneficiaries: Samsung, SK hynix, JEDEC standard
Rather than moving data to the compute unit, PIM brings computation to where the data lives. Samsung's HBM-PIM demonstrated the concept. The investment thesis hangs on JEDEC standardization — without a common standard, hyperscalers cannot build heterogeneous memory hierarchies at scale, and PIM stays confined to single-vendor deployments. JEDEC working group progress is the real signal. When a milestone lands, it is a valuation event for every memory producer with HBM-PIM exposure.
Track 4: 3D Memory-Logic Stacking | 2028–2030
Beneficiaries: TSMC, Samsung, Intel, Amkor, ASE
Stacking memory dies vertically above logic reduces the data-movement bottleneck by shortening the path to microns. This is HBM's architectural successor in the sense that it tightens the integration further — not a replacement for HBM in the current cycle. The foundry and packaging layer becomes the critical infrastructure node: TSMC's CoWoS, Intel Foveros, Samsung's advanced packaging roadmap. The company that controls the interposer controls the margin. This is why TSMC's advanced packaging capacity is a memory infrastructure story as much as a logic story.
Track 5: Optical Memory Interconnect | 2028–2030
Beneficiaries: Silicon photonics, co-packaged optics (Ayar Labs, Intel Silicon Photonics)
Optical interconnects solve the distance problem: copper traces limit HBM to within millimeters of the compute die; light can run across a rack. The memory-specific application is still early. But the co-packaged optics infrastructure buildout (Ayar Labs, Intel Silicon Photonics, Marvell) serves this market as a second-order beneficiary — the pipes being built for optical networking today are the same pipes that optical memory interconnect will use. Building position in CPO infrastructure now is a hedge on this track.
BAND 3 — POOL, TIER, AND COMPRESS
Track 6: CXL Memory Expansion and Pooling | 2026–2027 — NOW
Beneficiaries: Astera Labs, Montage, module/controller suppliers
CXL memory expansion is real today. Astera Labs' Leo CXL Smart Memory Controller and Montage's CXL Memory eXpander Controller are both shipping. The investment test is the second claim: rack-level pooling that meaningfully reduces hyperscaler DRAM demand at scale. That is still the thing to watch, not something to state as inevitable. The structural insight is this: Astera and Montage are not memory producers. They are interface tollbooths. If CXL pooling scales, they determine how much expensive DRAM the system actually needs — which means they participate in every dollar of memory savings without owning a fab.
Track 7: Predictive Tiering | 2026 — NOW
Beneficiaries: AMD / MEXT, enterprise SSD ecosystem
Software that predicts which data will be needed next and pre-promotes it from NAND into DRAM — before the compute unit asks for it. AMD's June 15 acquisition of MEXT is the clearest market signal that this technology has crossed the credibility threshold. AMD's stated rationale: improve memory optimization, reduce total cost of ownership, and make flash behave more like DRAM for compute infrastructure. The moat is application-specific tuning at a granularity that general-purpose OS memory managers cannot match. The risk is that compression gains front-load — first-generation deployments capture the easy 30%; subsequent gains require architectural changes that take longer.
Track 8: Algorithmic Compression / KV Cache Compression | 2026 — NOW
Beneficiaries: Inference software and model-efficiency layer
Model quantization, sparsity, and KV cache compression reduce the memory footprint of inference workloads without changing the underlying hardware. This is the fastest-moving track because it requires no new silicon and no new standards. A 70B parameter model at INT4 quantization consumes roughly one-quarter the DRAM of the same model at FP16 — that arithmetic happens in software today. The limitation: compression gains are model-specific and front-loaded. The first 30% comes easily. The next 30% requires fundamental architectural changes. This track extends the runway before hardware tracks arrive; it does not replace them.
Track 9: Module Innovation (MRDIMM, CAMM2, LPDDR-Based Server Modules) | 2026–2027
Beneficiaries: Module interface and controller IP owners
LPDDR5X-based server memory modules and next-generation RDIMM architectures (MRDIMM, CAMM2) expand effective server memory capacity without requiring HBM-tier capital. This is the least dramatic-sounding track and the most immediately deployable. The structural point: module makers who own the controller IP have pricing power in this cycle; those who are pure assemblers without interface IP do not. The standard (JEDEC CAMM2, MRDIMM) determines which layer captures economic rent.
BEYOND THE NINE — STRATEGIC WATCHLIST
Track 10: SRAM Inference ASICs | 2026 — Heavy capital inflow now
Beneficiaries: Groq, Cerebras, d-Matrix
Skip HBM entirely. SRAM-based inference ASICs hold the entire model in on-chip SRAM, achieving memory bandwidth that HBM cannot match at any price. The economics only work for specific, high-volume inference workloads — but for those workloads, the memory tax becomes irrelevant. The capital inflow is the signal: Groq and Cerebras are receiving heavy funding in 2026 because the market believes the memory tax stays elevated long enough to make the SRAM route economically durable. This is a Band 4 watch — not a near-term trade, but the outcome that caps the terminal multiple for HBM at some future point.
Track 11: New-Material Memory (FeRAM, MRAM) | 2030+ R&D stage
FeRAM and MRAM promise non-volatile memory with DRAM-class access speeds. Neither is near commercial scale for AI inference workloads. This is the terminal-state architecture — the one that makes the DRAM/NAND hierarchy obsolete — but it arrives after every other track has played out. Its investment relevance today is that it is the reason not to make permanent bets on any layer of the current hierarchy. Every moat in memory is provisional.
PART III: THE DYNAMICS OF THE BOARD
Front 1: Hyperscalers are starting to own the standard. AWS, Google, and Microsoft are writing JEDEC working group submissions, publishing CXL reference architectures, and funding controller IP startups. Every standard they influence is a margin decision — away from memory producers and toward platform providers. The CXL controller market (Astera Labs, Montage) is the clearest current example of a tollbooth that hyperscalers have not yet decided to internalize.
Front 2: Nvidia is seizing the entire memory hierarchy as interface. The H100 and H200 treat memory bandwidth as a product feature under Nvidia's architectural control — NVLink fabric, HBM stack, on-chip SRAM. The nine detour tracks are, in part, a response to the cost of renting that architecture at Nvidia's prices. SRAM inference chips are the most direct competitive threat. Every detour that routes around HBM is also a detour around Nvidia's interface control.
Front 3: The line between memory and foundry is collapsing. 3D memory-logic stacking and HBM both require the same advanced packaging infrastructure as leading-edge logic. TSMC's CoWoS capacity is a memory infrastructure constraint as much as a logic constraint. The interposer is where memory meets compute — and that interface is rapidly becoming the most contested margin layer in the semiconductor stack.
Front 4: The standards war decides where the margin sits. CXL, JEDEC HBM-PIM, CAMM2, and MRDIMM are not technical footnotes. They are contractual agreements about which layer of the stack captures economic rent. The company whose architecture becomes the standard for the interface between a detour track and the rest of the system extracts margin from every unit shipped — regardless of which medium is underneath.
WINNERS & LOSERS
LAYER | CLASSIFICATION | WHY IT MATTERS | KEY NAMES / RISK |
HBM scarcity winners | NEAR-TERM WINNERS | The same wafer math that creates the shortage creates the margin. HBM3E delivers outsized profitability for as long as the commodity floor is squeezed. This is the trade that is already working. | SK hynix (clearest HBM dominance), Samsung, Micron — risk: detour adoption begins to reduce commodity demand faster than expected |
NAND as AI memory adjunct | STRUCTURAL BENEFICIARIES | Six of the nine detour tracks route demand through NAND. HBF, NAND tiering, on-device inference, and module innovation all increase NAND attach rates in AI infrastructure. The market still prices NAND producers as storage companies. That is a mispricing. | Sandisk (SNDK — post-WDC separation), Kioxia, SK hynix, Samsung — risk: DRAM normalization reduces urgency for NAND substitution |
CXL / controller interface | EMERGING TOLLBOOTHS | Astera Labs and Montage are not memory producers. They are the companies that determine how much expensive DRAM the system actually needs. If CXL pooling scales at hyperscalers, they extract margin from every dollar of memory savings — without owning a fab. | Astera Labs, Montage — risk: hyperscaler internal development of CXL controllers; standards fragmentation |
Predictive tiering software | STRATEGIC SOFTWARE LAYER | AMD's MEXT acquisition validates the category. Application-specific tiering software that reduces DRAM demand has pricing power proportional to the DRAM it displaces — and DRAM is expensive. | AMD / MEXT, enterprise SSD ecosystem — risk: first-generation gains front-loaded; deep optimization requires architectural changes |
Advanced packaging / memory-compute interface | STRUCTURAL BENEFICIARIES | 3D memory-logic stacking and HBM both live on the same advanced packaging infrastructure. The interposer is where memory meets compute. Whoever controls CoWoS, Foveros, and equivalent platforms controls the interface margin. | TSMC, Samsung, Intel, Amkor, ASE — risk: capital intensity; capacity constrained by the same bottlenecks as leading-edge logic |
Foreign tools with China/CXMT optionality | NEAR-TERM WINNERS WITH POLICY RISK | CXMT's aggressive DUV buildout — and a reported $2.94B server DRAM supply deal with Tencent — generates near-term etch, deposition, and process tool demand that is not subject to the same export restrictions as EUV. Every CXMT fab adds incremental backlog. | Tokyo Electron (cleanest play — limited US policy exposure), Lam Research, Applied Materials — risk: US export control expansion to etch/deposition categories reverses tailwind immediately |
SRAM inference ASICs | STRATEGIC WATCHLIST | Skip HBM entirely. For specific high-volume inference workloads, SRAM chips eliminate the memory tax. Heavy capital inflow in 2026 signals the market believes the shortage is durable enough to fund the alternative. | Groq, Cerebras, d-Matrix — risk: market limited to specific workloads; DRAM normalization reduces urgency |
ASML | NARRATIVE WATCHLIST | EUV monopoly for planar DRAM scaling is intact. Near-term fundamentals are unaffected. The risk is terminal: if 3D DRAM architectures advance outside EUV's reach, the justification for an indefinitely premium multiple becomes more complicated — not eliminated, but complicated. | Risk is multiple compression, not fundamental impairment — but the two are connected at current valuations |
Micron Technology | CONTESTED WINNER | Micron benefits from HBM scarcity and industry-wide memory tightness — it is one of three HBM suppliers globally. The risk is not that Micron loses today. The risk is that investors pay a structural multiple for a shortage that CXL, NAND tiering, compression, and module innovation eventually route around. | HBM and tight supply are tailwinds now; commodity DRAM detour adoption is the medium-term multiple question |
PRESSURE POINTS
PRESSURE POINT | WHAT TO WATCH | TIME HORIZON |
AMD MEXT Integration Results | First real-world data on whether predictive tiering reduces DRAM consumption at AMD customers. Earnings call language around memory utilization efficiency is the leading indicator. | Q3–Q4 2026 |
CXMT / Tencent Server DRAM Ramp | Reuters reported a $2.94B long-term server DRAM supply deal between CXMT and Tencent. Execution on this contract is the first commercial proof point that Chinese domestic cloud customers will accept CXMT server-grade memory at scale. | 2026–2027 |
CXL Rack-Level Pooling at Hyperscalers | CXL expansion is shipping. The investment-grade question is whether rack-level pooling reduces measurable DRAM demand at AWS, Azure, or Google Cloud. Procurement guidance and memory attach-rate commentary are the signals. | Q3 2026 – Q2 2027 |
Sandisk / SK hynix HBF Standardization Milestone | OCP standardization for High Bandwidth Flash is underway. The first formal OCP approval or adoption announcement is the catalyst that moves HBF from roadmap to procurement reality. | 2027 |
JEDEC PIM Working Group | PIM/PNM scales only with a JEDEC standard. A milestone here is a valuation event for every memory producer with HBM-PIM exposure. Silence from JEDEC is a signal that Track 3 is slipping. | 2027–2028 |
3D DRAM Technical Demonstration | Any public proof of competitive density in 3D DRAM — by CXMT or any manufacturer — reprices equipment stocks and validates the EUV bypass thesis simultaneously. | 2027–2028 |
US Export Control Expansion | Tightening of DUV multi-patterning rules or etch/deposition tool restrictions would slow CXMT's buildout and shift the near-term capex beneficiary dynamic among Tokyo Electron, Lam, and Applied Materials. | Event-driven |
CREDIBILITY FIREWALL
COMPANY-DISCLOSED | MODEL-DERIVED | EDITORIAL VIEW |
HBM consumes wafer capacity vs. DDR5 at 3:1 ratio (Micron published figures). Conventional DRAM contract prices up 90–95% QoQ Q1 2026, further 58–63% expected Q2 2026 (TrendForce). | HBM wafer-start share rising from ~18% (2025) to ~30% (2027); bit share rising from ~8% to ~13% over same period (TrendForce/public capacity data). The wafer share move is 2x the bit share move — die size divergence is accelerating the real capacity erosion. | The wafer-start arithmetic is the entire setup. Bit share is the number analysts quote; wafer starts are the number that determines commodity DRAM supply. They diverge further every quarter HBM allocation rises. |
AMD acquired MEXT, memory-optimization startup, June 15, 2026 (public announcement). AMD stated rationale: improve memory optimization, reduce total cost of ownership, make flash behave more like DRAM (AMD official blog). | CXL memory expansion deployable in hyperscaler racks by 2026–2027 based on published platform roadmaps (Intel, AMD) and shipping controller silicon (Astera Leo, Montage MXC). Rack-level pooling adoption is unconfirmed at scale. | AMD did not buy a DRAM supplier. It bought a way to reduce how much DRAM customers need. In a normal memory cycle, that is an efficiency niche. In this cycle, it is a public admission that the memory hierarchy is no longer fixed. |
Sandisk and SK hynix announced High Bandwidth Flash global standardization effort under Open Compute Project, February 2026 (Sandisk press release). Standardization is underway; commercial deployment is 2027+. | CXMT server DRAM supply deal with Tencent reported by Reuters (June 29, 2026) at ~20B yuan ($2.94B) long-term; CXMT global DRAM share ~7.7% in 2025, capacity expansion to ~600K wafers/month planned (Reuters, citing sources). | The memory tax is being attacked from both sides: system architecture reduces demand (nine tracks), while China adds politically protected supply (CXMT/Tencent). Neither alone resolves the global shortage. Together they change who controls the price floor. |
Intel CEO stated no DRAM market stability until 2028 (public remarks). Analyst consensus: meaningful supply easing H2 2027 at earliest. | SK hynix Americas regional president and ASML employee flagged 3D DRAM efforts at Silicon Valley Korean Semiconductor Meetup (March 2026) — directional and non-official; treated as leading indicator, not confirmed disclosure. | The nine detour tracks are not competition among alternatives. They are division of labor across a time axis. Earliest relief (CXL, predictive tiering, compression) arrives before new fabs. Structural redesign (3D stacking, optical interconnect) arrives after. Interface owners — not medium owners — capture the durable margin. |
BEAR CASE SPOTLIGHT The nine detour tracks are slower than they look on a roadmap. CXL adoption requires platform support only available in next-generation server silicon. Predictive tiering works in controlled deployments and breaks in heterogeneous production environments. Algorithmic compression gains front-load — the first 30% comes easily; the last 30% requires architectural changes. HBF standardization is underway but commercial deployment is 2027+. JEDEC PIM standardization has no public timeline. And if AI investment bends faster than expected, the memory tax dissolves on its own before most of these tracks reach commercial scale — destroying the investment thesis for every company that raised capital against the elevated-price assumption. The CXMT factor cuts both ways: Chinese domestic DRAM supply adds commodity pressure that could accelerate the normalization timeline. |
FIVE THINGS TO DO WITH THIS INFORMATION
1. Watch AMD's MEXT integration closely. The first earnings call commentary that quantifies DRAM reduction at AMD customers is the earliest real-world proof point for the entire predictive tiering opportunity. When AMD talks about memory utilization efficiency, that is Track 7 in motion.
2. Reclassify NAND producers as AI infrastructure, not storage. Sandisk, Kioxia, and SK hynix benefit from six of the nine detour tracks. The market prices them as storage companies. That classification is wrong and it is a mispricing. Note: Sandisk (SNDK) is the correct ticker for flash exposure post the 2025 WDC separation; Western Digital is now a separate HDD/mass-storage entity.
3. Treat CXL controller IP as infrastructure, not components. Astera Labs and Montage are not memory companies. They are the companies that determine how much memory everyone else needs to buy. The distinction matters for valuation — tollbooths deserve a different multiple than commodity suppliers.
4. Monitor JEDEC PIM working group progress. The standard determines whether Track 3 (PIM/PNM) reaches commercial scale in 2028 or 2031. A JEDEC milestone is a valuation event for every memory producer with HBM-PIM exposure. Silence from JEDEC is a signal that the track is slipping.
5. Do not anchor on the 2027 supply-normalization consensus without pricing in demand reduction. The consensus assumes supply recovers in H2 2027. It does not account for nine detour tracks reducing demand in the same window. If both arrive simultaneously, normalization is faster and sharper than models expect — and positions sized on a prolonged shortage thesis need to reflect that two-sided risk.
The AI Buildout Has a Physical Layer
Many of today’s data centers are still using copper wiring. The same metal we’ve been using for a hundred years.
At the speeds AI demands with data moving between thousands of GPUs, billions of times a second, copper doesn’t just slow down.
It turns that data into heat. The more you push through it, the worse it gets. There’s no software for fix for that.
So what’s the answer?
Explore the Photonics Layer…..
Tuttle Capital Pure Play Photonics ETF (FOTO)
Distributor: Foreside Fund Services | Investing involves risk including possible loss of principle.
News vs. Noise: What’s Moving Markets Today
I’ve been suggesting adding a bit to hedges. This is not a top call, it’s a short term tactical call. Today looks like we may see a momentum selloff, especially in memory, but it’s early.
The news. The AI memory supercycle is real. The market still wants to call it cyclical because memory has always been cyclical. That may be the wrong playbook. Micron disclosed 16 strategic customer agreements, most covering 2026 to 2030, and Sanjay Mehrotra said customers recognize that memory and storage shortages will take “considerable time to improve.” He also said Micron has no line of sight on when supply catches demand. That is pricing power. Apple is the tell. MarketWatch says Apple is looking for approval to use CXMT chips after memory costs forced MacBook and iPad price hikes. This is not just a Micron story. It is an AI infrastructure bottleneck story. The second piece of news is the yen. Reuters says the dollar hit 162.66 yen, the weakest since 1986, after Japan spent 11.7 trillion yen in April and May defending the currency. Tokyo is not fighting speculators. It is fighting the Fed. The Register, MarketWatch, Reuters.
The noise. The noise is that payrolls, JOLTS, and oil at $70 have somehow made the Fed and Hormuz less important. They have not. MarketWatch says Warsh speaks at Sintra at 9 a.m. ET, and investors are waiting for his read on inflation and the economy. Reuters says Cleveland Fed President Beth Hammack is still willing to argue for higher rates if inflation does not cool, and she said every meeting is live. That is the regime. No forward-guidance crutch. No automatic pivot because one labor print softens. Same problem in oil. Reuters says analysts cut oil forecasts because Hormuz reopening eased supply fears. But The Guardian reports the U.S. and Iran have not had direct talks since the deal, only 60 days were set aside, both sides traded fire over the weekend, and Iran’s negotiator said traffic in the strait is subject to arrangements determined by Iran. That is not resolved. That is a live option with a lower price tag. MarketWatch, Reuters, Reuters, The Guardian.
The dumb advice. The dumb advice is assuming “normal” shipping through Hormuz and building an oil forecast on top of it. Reuters quoted LBBW’s Frank Schallenberger saying, “If traffic through the Strait of Hormuz comes back to normal, we will go back to supply surplus on the oil markets.” That is the problem. The word “if” is doing all the work. The Guardian says 40 ships transited Monday, up from 24 the prior day, but hundreds of vessels remain stranded and traffic remains far below normal. It also says Iran is fighting outside demining, wants control over arrangements, and may use the current level of traffic to keep pressure on oil prices. That does not mean oil has to rip tomorrow. It means the market is treating a fragile reopening as a permanent supply reset. The Red Sea taught the opposite lesson. A ceasefire can stop headlines and still fail to normalize flows. Reuters, The Guardian.
Concrete takeaways.
Memory is the cleanest AI bottleneck. Treat it like scarcity until supply proves otherwise.
Semis are not broken. The easy phase is over. The selective phase is here.
Apple’s memory problem is a signal, not a one-off product-pricing story.
Yen weakness is not just Japan’s problem. It is a Fed/carry-trade problem.
Hormuz is paused, not solved. Oil is pricing a smoother path than the facts support.
Do not build a portfolio on “if traffic normalizes.” Own the chokepoints. Fade the assumptions.
Where Does the Money Go When AI Hits a Wall?
When capital chases a tech theme, it tends to pile into the most obvious
layer and miss the one underneath. AI spending is now bumping hard
against memory. Hyperscalers — the big cloud builders like Amazon,
Google, and Microsoft — have shifted memory from 8% of their build
budgets to an estimated 30% in a single cycle. That capital has to go
somewhere. If the constraint is memory, and the build can't move without
it, shouldn't an investor own the layer AI runs on?
View HBMX fund holdings →
Distributor: Foreside Fund Services | Investing involves risk including
possible loss of principal.
<Link = http://www.hbmxetf.com/>
ETF News
A Stock I’m Watching
Sold off on Friday, most likely on removal from the Russell 2000, now an undercut and rally at the 50 day.
Bloom Energy has evolved from a “clean energy/fuel cell” story into a power-for-AI infrastructure story, and the latest catalyst is big: Bloom and Brookfield just expanded their AI infrastructure financing partnership from $5B to $25B, specifically to fund rapid power projects for AI data centers, with Bloom citing strong hyperscaler and AI-infrastructure demand for its islanded onsite power systems. (Bloom Energy) That follows the Oracle expansion in April, where Oracle agreed to procure up to 2.8 GW of Bloom fuel-cell systems, with an initial 1.2 GW already contracted and deployment underway across U.S. projects. (Bloom Energy) The numbers are now validating the story: Q1 revenue was $751.1M, up 130.4% year over year, product revenue was up 208.4%, and management raised 2026 revenue guidance to $3.4B-$3.8B, implying roughly 80% growth at the midpoint. (Bloom Energy) The setup is that investors are aggressively looking for AI infrastructure bottleneck plays beyond semis, and BE offers direct exposure to the “time-to-power” problem for data centers; while the stock is no longer cheap and has already moved, the combination of major strategic capital, Oracle-scale demand, accelerating revenue growth, and expanding margins makes BE a credible momentum buy candidate on any pullback or continued AI-power bid.
In Case You Missed It
Great conversation on wide ranging topics with Kenny Polcari…
The H.E.A.T. (Hedge, Edge, Asymmetry and Theme) Formula is designed to empower investors to spot opportunities, think independently, make smarter (often contrarian) moves, and build real wealth.
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